AMD Venice-X Returns 3D V-Cache to Data Center with 5.3 GHz Boost

AMD's Venice-X will bring 3D V-Cache back to its data center EPYC lineup for HPC workloads, pairing 96 cores and 1,152 MB of L3 cache with a 5.3 GHz boost clock. The chips are expected to use the SP7 socket with PCIe 6.0 and up to 1.6 TB/s of per-socket memory bandwidth, and AMD says they will launch in the second half of 2027.

Return of 3D V-Cache

AMD missed deploying Turin-X in the previous generation, giving 3D V-Cache a four-year hiatus from the data center after Genoa-X launched in 2023. Venice-X matches the 96 cores and 1,152 MB of L3 cache of the EPYC 9684X, but adds much higher clock speeds. AMD also says the chip uses the full 16-channel SP7 memory setup, including MRDIMMs at 12,800 MT/s.

Frequency and cache

Unlike the standard SP7 lineup, the big change is not a large jump in core count or cache. Venice-X reaches the family maximum 5.3 GHz boost clock, combining high frequency with stacked L3 cache for HPC. 'You can get the best of both worlds in a single CPU,' said AMD Fellow Phil Steinke.

Workloads and benchmarks

AMD says functional verification workloads make up over half of its used HPC compute, and that a workload completes 40% faster with 3D V-Cache at around double the instructions per clock. The company also compared its high-frequency EPYC 9686F with Intel's Xeon 6980P, saying the AMD chip was 1.6x faster in several HPC benchmarks while running 32 fewer cores. AMD plans to keep using MEXT, its AI-driven flash-as-DRAM technology, when it deploys Venice-X.

Open details

Several details remain unknown, including the base frequency, the number of SKUs, and the exact TDP. AMD lists the TDP as unknown, though the 400 to 600 W range available to other Venice CPUs is likely. Verano, pitched as an AI host node using SOCAMM2 LPDDR5X memory, is also coming in the second half of next year.

Sources: Tom's Hardware