Nagare Labs' Z2RAM aims for SRAM speed and DRAM density

Nagare Labs, a Georgia Tech spinout backed by Pat Gelsinger, says its Z2RAM memory can place SRAM-speed memory at DRAM density directly on AI chips. Published cells from its founders have retained data for more than 300 seconds at 85 degrees Celsius. The company's Gen 1 figures, including 5x SRAM density and 14x DRAM speed, remain projections.

How Z2RAM works

Nagare describes Z2RAM as "Two transistors and a shield. No capacitor." A write transistor places charge on a storage node, the shield blocks noisy neighbors, and the read transistor can sense without draining. In this gain cell, the read transistor's gate capacitance holds charge, so reads are non-destructive and avoid DRAM write-back. Nagare aims for well under a picojoule per bit.

The memory bottleneck

AI chips need high bandwidth, but HBM yields are challenging. Heat also limits stacked memory, and Samsung's zHBM is planned at about four layers. Nagare says peak compute has grown 70 percent a year over three decades, against 20 percent for memory bandwidth. A 2025 simulation by co-founder Shimeng Yu's group put logic power under stacked DRAM at 220 W/cm2, or 300 W/cm2 with better thermal vias, to keep DRAM at or below 95 degrees Celsius.

Published results and open questions

A 2020 paper from co-founder Suman Datta's group reported 1 second retention at 25 degrees Celsius and 300 milliseconds at 85 degrees Celsius. A 2025 update managed more than 1,000 seconds at 25 degrees Celsius, and a later boosted three-transistor cell held data for more than 300 seconds at 85 degrees Celsius. That is still below the roughly 95 degrees Celsius that Nagare says DRAM must stay under, so neither the founders' published cells nor Z2RAM itself have shown retention above that line. Nagare declined to share measured retention, latency, or energy figures. Datta told The Register that sampling of Z2RAM tiles is targeted within four years and production shipments, if they arrive, within the next decade.

Manufacturing hurdles

Nagare builds layers on top of the accelerator and patterns them together on one die, with no interposer or bonds between memory layers. It currently has no fab and is looking for an R&D fab partner. Yu told The Register that no standard exists for integrating this kind of memory with an accelerator, and Datta cited reliability concerns such as single-electron effects.

Sources: Tom's Hardware