IBM unveils first sub-1 nanometer chip technology

IBM said on June 25 that it has built the world's first sub-1 nanometer chip technology, a transistor architecture at the 0.7 nm — or 7 angstrom — node. The company presented the work as a landmark for an industry that has been approaching the physical limits of conventional scaling.

The chip packs nearly 100 billion transistors onto a piece of silicon the size of a fingernail, roughly twice the density of IBM's 2 nm chip, which the company unveiled in 2021. Published technical results project up to 50 percent more performance, or 70 percent greater energy efficiency, than IBM's 2 nm node chips — gains aimed at workloads such as generative AI and cloud infrastructure.

The nanostack architecture

To get there, IBM researchers developed a new transistor design called “nanostack”, which the company describes as the industry's first known three-dimensional, nanosheet-based architecture. It builds on nanosheet technology, the current leading-edge approach that IBM itself invented, by vertically stacking and staggering transistors and using 3D sequential integration to fit more of them onto a chip.

The design also allows different material combinations within each stacked layer, so the performance and power characteristics of one transistor can be tuned independently of another. IBM says the architecture was experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering, and functional CMOS inverter operation with the expected switching performance — evidence that the structure can be built and can compute.

Separately, research presented at VLSI 2026 showed that nanostack delivers 40 percent scaling in SRAM, which matters for chip designers trying to serve the high-bandwidth demands of advanced AI workloads.

Why it matters

With this structure, IBM says logic technology can extend below the 1 nm node for the first time, into angstrom-level scaling where dimensions approach the size of individual atoms. Node names today refer to a generation of manufacturing technology rather than a precise physical dimension, but IBM's roadmap projects at least a decade of further scaling on the nanostack path.

“We're not just making smaller transistors, we're reinventing how chips are built,” said Jay Gambetta, Director of IBM Research and IBM Fellow. He describes the result as pushing computing beyond the nanometer era to the scale of atoms.

The work is carried out with partners at a semiconductor research facility in Albany, New York, which will soon house a High Numerical Aperture EUV lithography tool from ASML — equipment IBM calls essential to future logic scaling. Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions are among the partners developing High NA EUV processes and tools that have already produced working devices. IBM expects the earliest adoption of nanostack at the sub-1 nm node to reach production in as little as five years.