Micron Plans Wafer Bonding and High-NA EUV for Next-Gen DRAM

Micron plans to use wafer bonding and High-NA EUV lithography for future DRAM, after dropping 4F2 memory cells from its roadmap. The company is also developing vertical high-bandwidth memory and vertical edge inference memory, which will sit directly on top of processors. Micron says future DRAM scaling will rely on new process technologies and closer integration with logic chips.

Process roadmap

Micron's current 1γ DRAM process is in high-volume manufacturing, while 1δ is scheduled for volume production in the second half of 2027. The 1δ process promises a mid-20% increase in bit density and is optimized for future AI memory products, including HBM5, vHBM, and vEIM. Beyond that, Micron plans to introduce wafer bonding with its 1ε process, which is under development. For later generations, ζÅ and ηÅ, the company plans to adopt High-NA EUV lithography and new materials to continue shrinking DRAM cells. Micron is also collaborating with Albany NanoTech on fabrication technologies for the next five to 10 years. Scott DeBoer, president and chief technology and products officer at Micron, said DRAM is nearing atomic limits at this point, and that the company is focused on introducing 3D DRAM at the optimal time from a cost and performance point of view.

3D DRAM plans

Micron lists two 3D DRAM generations, 3D1 and 3D2, on its roadmap. It has not disclosed their architectures or launch schedules. The company says it will introduce 3D DRAM only when the technology offers sufficient advantages in manufacturing costs, complexity, and performance over conventional planar DRAM. Micron's CTO said the technology is a parallel path and will be implemented in a way that is ideal for cost, complexity, and device performance.

Vertical memory

vHBM will place memory stacks directly on top of processors such as AI accelerators and AI GPUs, rather than next to them. This promises substantially lower latencies and higher bandwidth through shorter connections, but it also creates significant thermal challenges and limits the number of memory stacks that can be placed on top of an ASIC. Micron expects vHBM to complement conventional HBM, which will continue to provide the bulk of memory capacity in many AI accelerators.

vEIM shares architectural and packaging characteristics with vHBM but targets energy efficiency for edge AI processors used in autonomous vehicles, robotics, and other power-constrained devices. Even first-generation vEIM targets 2 TB/s bandwidth at less than 1 pJ per bit, which Micron says is in line with what HBM4 currently offers at 8 GT/s over a 2,048-bit interface. Micron intends to optimize these products with customers based on bandwidth, capacity, and power requirements.

Packaging and industry impact

Both vertical memory architectures will require advanced packaging, particularly hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management will be critical, especially for vHBM, and Micron is developing specialized heat-spreading structures to move heat from hot regions of memory base dies through the DRAM stacks. The company has not disclosed when vHBM, vEIM, or custom HBM will enter commercial production. Micron says future memory performance improvements will increasingly depend on advanced packaging and closer integration with processors, requiring collaboration between DRAM makers and logic developers. This shifts memory from a commodity to a critically important ingredient of an ASIC design.

Sources: Tom's Hardware