The state of SIMD in Rust in 2026: crates mature, intrinsics still hurt

Sergey Davidoff published his annual survey of SIMD support in Rust on September 25, 2026. SIMD, or single instruction multiple data, lets a CPU apply one arithmetic operation to a whole packed batch of numbers: on recent x86 chips these vectors reach 512 bits, which in theory allows up to 8x faster math on f64 and 64x on u8.

The author became a maintainer of Fearless SIMD after last year's survey, so to avoid a conflict of interest he asked the authors of std::simd, wide, pulp and macerator to review a draft, while keeping editorial control. His conclusion is that support has matured a great deal, and that Rust is now attractive for SIMD code even when memory safety is not a hard requirement.

x86 fragmentation and multiversioning

On x86_64 the compiler may only assume SSE2 by default, so anything newer has to be selected at runtime. AVX2 launched in 2013, yet the most recent Intel CPU without it shipped in 2021, and 15% of x86 systems in the Firefox hardware survey still lack it in 2026. The standard answer is multiversioning: compile the same function for several SIMD levels and pick one after checking the CPU features. The multiversion crate does that with a single attribute, although it adds overhead to very small functions. ARM made NEON mandatory on 64-bit cores, so the problem is essentially x86-only.

Portable SIMD crates

std::simd sits directly on LLVM and can target anything LLVM supports, but it is nightly-only. When LLVM has no matching operation, the code silently falls back to scalar math, which the author calls the cardinal sin. Fearless SIMD shipped version 1.0 with a security policy: it hides far less unsafe code than its peers and makes multiversioning work even for tiny functions. wide covers many operations including trigonometry, but cannot be combined with multiversioning. pulp powers the faer linear algebra library, and macerator is the CPU backend of burn.

Intrinsics and hardware

Since Rust 1.87 platform intrinsics can be called safely through target features and feature tokens such as those in the archmage crate. Even so, intrinsics remain the weak spot: the compiler often fails to lower them into the intended instructions, and the author documents a case where an “optimization” made a 512-bit shuffle slower than the instruction he asked for, fixed in LLVM 23 after his report. On the hardware side, early Intel CPUs with AVX-512 downclocked the whole chip, a behaviour fixed only with Ice Lake in 2019, while Steam's survey puts AVX-512 at 23.9% of systems. Trigonometry is the biggest remaining gap.