The vfmaddrnd231pd Instruction: Documented in Intel SDM but Never Built

The Ghost Instruction

vfmaddrnd231pd appears in Intel's Software Developer's Manual (SDM) as a member of the FMA instruction set. According to the 2024 edition of the manual, it performs a fused multiply-add of packed double-precision floating-point values with rounding control. An immediate byte attached to the instruction defines several bit fields that control rounding, DAZ, FTZ, and exception suppression. Such per-instruction rounding control would let arithmetic operations choose their rounding mode directly, instead of relying on the slow-to-change global settings, and could make rounding dependent algorithms significantly faster. Except the instruction does not exist.

Failed Searches and a #UD Error

The GNU assembler does not recognize vfmaddrnd231pd. The SDM lists the Intel C/C++ Compiler intrinsics _mm_fmaddround_pd and _mm256_fmaddround_pd, but those are absent not only from Clang but from ICC as well. Assembling the instruction manually from the SDM opcode list, VEX.DDS.128.66.0F3A.W1 B8 /r /ib, raises another question: the manual contains no other mention of what DDS means. Executing the instruction on a Haswell CPU, which does support the FMA instruction set, raises a #UD (undefined instruction) error. The 2026 edition of the SDM no longer lists the instruction, although the 2024 edition does, and it lists no sibling variants such as the pd, ps, sd, ss or 132, 213, 231 forms that other FMA instructions have.

An AVX10 Prototype Left Behind

Comments on the original blog post filled in the history. In 2023 Intel failed to add AVX-512 support to consumer CPUs due to hardware limitations, but still wanted to ship some AVX-512 style features, which led to AVX10, an extension that resembled AVX-512 but conditionally supported 512 bit vector lengths. AVX-512 uses the EVEX prefix, whose bits for the static rounding mode are reused for operation width, so only scalar and 512 bit operations can customize rounding. AVX10, initially without 512 bit support, needed a different encoding for custom rounding modes. The theory is that Intel originally planned an immediate byte controlling rounding, which is how vfmaddrnd231pd and similar instructions came to be documented. It uses a VEX prefix rather than the AVX-512 specific EVEX prefix, which would let CPUs without 512 bit vectors ignore EVEX entirely. By 2024 Intel decided the approach would not work and instead dedicated the last unused bit in the EVEX prefix to enabling rounding modes for 256 bit vectors, reusing the AVX-512 encoding and assembly syntax, which made the vfmaddrnd231pd mnemonic and its siblings unnecessary. During the rework, someone forgot to remove the ghost instruction from the SDM draft.

Compiler Patches Confirm the Story

By 2025 AVX-512 was considered table stakes following the popularity of Zen 4, and Intel made 512 bit support unconditional in AVX10. The updated AVX10 whitepaper removed references to a 256 bit maximum vector register size and to 256 bit instructions supporting embedded rounding. Intel also submitted patches to GCC removing 256 bit rounding support, including one titled Revert "AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins", which removed multiple intrinsics such as _mm256_fmadd_round_pd, named very similarly to the intrinsic documented for the ghost instruction, _mm256_fmaddround_pd. At a later point, someone at Intel apparently noticed that vfmaddrnd231pd was still mentioned in the SDM and removed it. In the author's summary, the instruction is of AVX10 lineage: added during the prototyping stage, reworked to use a different encoding, and finally made unnecessary, yet accidentally published in an official manual for released hardware that never implemented it.

Sources: purplesyringa.moe