An embedded engineer from Trinidad answers the RISC-V critique

Embedded systems engineer Armstrong Subero has published a response to Dmitry Grinberg's essay "RISC-V: They Should Have Known Better", which reached the front page of Hacker News and set off a debate on Lobsters. Subero, who works from Trinidad and Tobago and says he moved his entire stack from STM32 and ARM to RISC-V, argues that the most important part of the critique is not about instruction encodings but about who can get hardware at all.

Points he accepts

Subero concedes several criticisms before arguing. He writes that RISC-V's compressed store offsets are strange, that Zicsr should not be an extension designers have to remember to request, and that he has run into all of these on the CH32V003 — one of the low-cost RV32E-class chips Grinberg mentions. He also notes that RISC-V International denied him membership and says he is not defending the ISA committee. But he observes that Grinberg's own list of what a cheap microcontroller core needs — low interrupt latency, small die area, good code density, no divider, no privilege separation — describes the instruction set that ten-cent chips already implement.

The shipping argument

The core of the reply is logistics. Working from Trinidad and Tobago, a small island nation off the coast of Venezuela, Subero says ordering a development board means checking whether a seller ships there at all and what the total comes to in local currency. Free shipping from Digikey, Mouser or European manufacturers does not apply to him: he pays between 60 and 200 US dollars to ship chips that cost about a dollar. A PCB company that had approached him about sponsorship, he adds, turned him down solely because of his location. For a class of thirty students, he argues, the difference between a ten-cent part and a one-dollar part is the difference between everyone having a chip and everyone watching a single demo board.

One ISA, two product boundaries

Subero also disputes the claim that opposed requirements make one instruction set impossible at both ends of the market. He lists parts he has used, from the ten-cent CH32V003 to the dual-core CH32H417 and the Baochip-1x, a chip with an MMU that runs the Rust microkernel Xous, seL4 and Linux. On ARM, he writes, the boundary between a small core and one with an MMU is not an architectural fact but a product boundary enforced by licensing: virtual memory means licensing a Cortex-A part. On RISC-V, supervisor mode and paging are optional features an implementer can switch on. He puts the cost of his own stack at under 100 dollars, against about 600 dollars for a single Segger J-Link debugger for ARM parts.

Fragmentation as the trade-off

On fragmentation he partly agrees: the split of Zcb from C and the optional status of Zicsr are annoying, and vendor-specific interrupt hardware fragments the ecosystem further — something he learned porting NuttX to the WCH CH32V307. Yet he argues the extension mechanism is precisely what lets one base instruction set serve both a sixteen-register ten-cent part and a chip running a protected operating system.