
Go 1.27 Adds an Experimental Platform-Independent SIMD Interface
The Go team has introduced an experimental simd package that hides the differences between processor architectures. Vectorized code written once now runs anywhere, and on platforms without hardware SIMD the operations are emulated.
Go 1.27 introduces an experimental SIMD interface that behaves the same way across processor architectures, the Go team's David Chase and Junyang Shao wrote in a blog post published on 24 September 2026. Until now, developers who wanted SIMD in Go had to write assembly or use architecture-specific APIs.
SIMD lets a single instruction act on a whole vector of values, such as adding eight pairs of float64 numbers at once. It speeds up cryptography, data processing and AI, and Go's Green Tea garbage collector already uses it to scan memory for live objects.
A portable layer over archsimd
Go 1.26 brought a SIMD API for amd64, and Go 1.27 added arm64 (NEON) and wasm. Those APIs live in archsimd, an architecture-dependent package, because platforms differ not only in the operations they offer but in how vectors are represented: some provide fixed-size vectors between 128 and 512 bits, while on others the size becomes known only when the program starts.
The new simd package, loosely based on Highway for C++, removes fixed-size vectors from the type system and keeps only operations available on every platform, filling the gaps with emulation built from other SIMD instructions. Its vector types are capitalized, plural primitives such as simd.Uint8s or simd.Float32s. Comparisons return masks tied to the element width, so comparing Int8s produces Mask8s. A ToArch() method bridges to platform-specific types, simd.<SimdType>FromArch converts back, and GOEXPERIMENT=simd enables the experiment.
Why platforms differ
wasm, PowerPC and s390x have one fixed vector size (128 bits), amd64 offers three (128, 256 and 512) and loong64 two. RISC-V length is unknown at build time, arm64 pairs fixed 128-bit NEON with variable-width SVE, and masking splits three ways: vector bitmasks, dedicated mask registers, or one mask bit per vector byte.
Emulation and dispatch
Many gaps need only two or three instructions: scalar shifts are emulated with vector shifts, and missing unsigned comparisons become a signed comparison plus two XORs with a constant. Carryless multiply, important for cryptography and CRC checksums, is emulated in constant time, and on hardware without SIMD support every operation is emulated so the code still runs.
GODEBUG settings let developers test specific hardware profiles: simd=0 forces emulation, simd=128, 256 and 512 select a vector width and panic when features are missing, and the +128, +256 and +512 forms tolerate missing features, as on Raspberry Pi (NEON without PMULL). An AST rewrite in the compiler front end specializes functions that mention simd types, and wrappers switch on the SIMD level detected at startup, avoiding per-operation dispatch.
What comes next
Go 1.28 should add OnesCount, mask, reduction and vector shuffling operations, plus SVE support for archsimd and hopefully for simd, along with a small set of feature variants that avoid full emulation on machines missing only one or two instructions. ReduceSum will also arrive, replacing the manual store-and-sum loop the current API requires.
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