RISC-V: an engineer's detailed critique of the architecture

Engineer Dmitry Grinberg has published a long essay on his blog dmitry.gr under the title "RISC-V: They Should Have Known Better", collecting in one place the arguments behind his scepticism toward the open instruction set architecture. He says he wrote it so that the next time he is asked to explain his position, he can answer with a link.

One architecture cannot serve everyone

No ISA can be best for every use case, and the needs of a high-end core are diametrically opposed to those of a small cost-saving microcontroller. Grinberg expects RISC-V to take over the cheap single-use microcontroller space now held by the 8051 eventually — but despite its ISA design rather than because of it. Interrupt handling illustrates the problem: a spec-compliant path requires the Zicsr extension plus mscratch or sscratch registers, and by his count it costs at least 44 cycles before a C handler does any work. Cortex-M0 enters an interrupt in 15 cycles and exits in 12, or 27 in total, because it pushes the ABI-clobbered registers in hardware. Even the reduced-register RV32E variant lands at 38 cycles, more than a third slower. The existence of CLIC and vendors' proprietary fast-IRQ extensions is, he writes, an additional indictment: the base ISA forces vendors to build non-standard silicon to reach parity with a decade-old core.

Compressed instructions and array access

The compressed extension is, in his view, poorly designed. A 16-bit store-byte instruction can encode offsets from zero to three only, store-halfword offers zero or two, store-word allows zero to 124. Cortex-M0 permits offsets of zero to 31 for bytes and zero to 62 for halfwords. The byte and halfword stores are not even part of C, but of a separate Zcb extension. The second problem is indexed addressing: x86 has [ebx + esi * 4] and ARM has [R0, R1, LSL #2], while RISC-V needs three instructions for a single array access. The usual excuse that fast cores will fuse them into one is weak, he argues, because no known core fuses more than two consecutive instructions. The Zba extension with its SHxADD instructions was ratified only in 2021, more than two years after the base specification.

Everything is optional

Grinberg compares RISC-V to USB-C and RCS: claiming compliance with the standard means almost nothing, because almost everything is optional. Multiplication is optional, division is optional, user and supervisor modes are optional, CSRs are optional, compressed instructions are optional. The CSRs that were originally part of the base instruction set were moved into the Zicsr extension, so the base ISA today can neither handle interrupts in a standard way nor separate privilege levels. The register meant to answer whether a feature is implemented is misa — itself a CSR, with optional support, and allowed to read as all zeroes. The same applies to the system timer, which is memory-mapped at an implementation-defined address, and to both interrupt vectoring modes, neither of which is mandatory.